Non-linearity in the phase-detector (PD) and charge-pump (CP) of a DSM based fractional-N PLL causes spurious tones (hereinafter referred to as “spurs”) in the output clock of the DSM based, fractional-N PLL. This is a well-known problem associated with this PLL architecture and is commonly addressed by: (1) ensuring that the PD and the CP are designed to be as linear as possible; and (2) reducing the PLL bandwidth to attenuate spurs. A block diagram of a well-known DSM based fractional-N PLL architecture is shown in FIG. 1.
Another well-known DSM based fractional-N PLL architecture is a dual-path, hybrid analog-digital DSM based fractional-N PLL architecture. The dual-path, hybrid analog-digital DSM based fractional-N PLL architecture breaks the loop-filter into two separate paths that operate in parallel, which allows for separate design of the proportional control path (high-bandwidth path) and integral control path (low-bandwidth path). A problem with known dual-path, hybrid analog-digital DSM based fractional-N PLL architectures is that non-linearity in each path contributes to in-band spurs.
Improvements in dual-path, hybrid analog-digital DSM based fractional-N PLLs are therefore desirable.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present invention.